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| general description the max6876 eeprom-configurable, multivoltage power tracker/supervisor monitors four system voltages and ensures proper power-up and power-down condi- tions for systems requiring voltage tracking and/or sequencing. the max6876 provides a highly config- urable solution as key thresholds and timing parame- ters are programmed through an i 2 c interface and these values are stored in internal eeprom. the max6876 also provides supervisory functions and an overcurrent detection circuit. the max6876 features programmable undervoltage and overvoltage thresholds for each input supply. when all voltages are within specifications, the device turns on the external n-channel mosfets to either sequence or track the voltages to the system. all of the voltages can be sequenced or tracked or powered up with a combination of the two options. during tracking, the voltage at the gate of each mosfet is increased to slowly turn on each supply. the voltages at the source of each mosfet are compared to each other to ensure that the voltage dif- ferential between each monitored supply does not exceed 250mv (typ). tracking is dynamically adjusted to force all outputs to track within a ?25mv window from a reference ramp; if, for any reason, any supply fails to track within ?50mv from the reference ramp, a fault output is asserted, the power-up mode is terminated, and all outputs are powered off. power-up mode is also termi- nated if the controlled voltages fail to complete the ramp- up within a programmable fault timeout. the max6876 features latch-off and autoretry modes to power on again after a fault condition has been detected. other features of the max6876 include a reset circuit, a manual reset input ( mr), and a margin disable input (margin). the device also features outputs for indicat- ing a power-good condition (pg_) and an overcurrent condition (oc), and a bus-removal (rem) output. the max6876 is available in a small 6mm x 6mm, 36- pin thin qfn package and is fully specified over the extended -40? to +85? temperature range. applications features ? tracking/sequencing for up to four supply voltages (with one max6876 device) and tracking for up to 16 supply voltages (using four max6876 devices) ? eeprom-configurable tracking/sequencing control ? bus voltage independent operation (max6876 is powered from the tracked supply voltages or always-on supply) ? eeprom-selectable undervoltage/overvoltage- lockout thresholds for each input supply ? eeprom-selectable power-up/down slew rate ? programmable power-good output thresholds and timing ? global adjustable undervoltage lockout or logic enable input ? independent internal charge pumps to enhance external n-channel fets (v gate_source = 5v) ? post power-up selectable overcurrent detection ? 0.5v to 5.5v in_ threshold range ? ?.5% threshold accuracy ? i 2 c/smbus -compatible serial interface ? small 6mm x 6mm, 36-pin thin qfn package max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit ________________________________________________________________ maxim integrated products 1 in4 gate4 refin n.c. pg2 pg1 pg4 pg3 out4 abp trken synch oc rem fault v cc 1 2 3 4 5 6 7 8 9 27 26 25 24 23 22 21 20 19 mr sda scl a1 n.c. margin enable reset gate1 out1 in2 gate2 out2 in3 gate3 out3 in1 6mm x 6mm thin qfn max6876 top view hold a0 gnd 36 35 34 33 32 31 30 29 28 10 11 12 13 14 15 16 17 18 ep* *exposed paddle pin configuration ordering information 19-3479; rev 0; 10/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin- package pkg code MAX6876ETX -40? to +85? 36 thin qfn t3666-3 multivoltage systems networking systems telecom storage equipment servers/workstations smbus is a trademark of intel corp.
max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages are referenced to gnd, unless otherwise noted.) gate_.............................................................-0.3v to (in_ + 6v) in1 in4, v cc ............................................................-0.3v to +6v out1 out4, synch, abp, refin...............................-0.3v to max (in1 in4, v cc ) + 0.3v enable, trken, hold , fault , mr , margin ......-0.3v to +6v reset , pg1 pg4, oc , rem....................................-0.3v to +6v sda, scl, a0, a1.....................................................-0.3v to +6v input/output current (all pins except out_ and gnd) ...20ma out_, gnd current..........................................................50ma continuous power dissipation (t a = +70 c) 36-pin, 6mm x 6mm thin qfn (derate 26.3mw/ c above +70 c) ..............................2105mw operating temperature range ...........................-40 c to +85 c storage temperature range .............................-65 c to +150 c maximum junction temperature .....................................+150 c lead temperature (soldering, 10s) .................................+300 c electrical characteristics (v cc , in1 in4 = +2.7v to +5.5v; enable = margin = mr = abp = trken; t a = -40 c to +85 c, unless otherwise specified. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units gate_ = pg_ = reset = 0 1.4 operating voltage range (note 2) v cc voltage on abp (from v cc or in1 in4) to ensure the device is fully operational 2.7 5.5 v undervoltage lockout v uvlo minimum voltage on abp (from v cc or in1 in4) to ensure the device is eeprom configured 2.5 v v cc = 5.5v, in1 in4 = 3.3v, no load 1.8 3 supply current i cc configuration registers or memory access, no load 2.5 4 ma in1 in4 (in 20mv increments) 1.00 5.50 in_ threshold range v th in1 in4 (in 10mv increments) 0.50 3.05 v t a = 0 c to +85 c 0.5v < in_ < 5.5v, in_ falling for uv, rising for ov -1.5 +1.5 % 2v < in_ < 5.5v, in_ falling for uv, rising for ov (20mv increments) -2.5 +2.5 % 1v < in_ < 2v, in_ falling for uv, rising for ov (20mv increments) -50 +50 mv 1v < in_ < 3.05v, in_ falling for uv, rising for ov (10mv increments) -2.5 +2.5 % threshold accuracy t a = -40 c to +85 c 0.5v < in_ < 1v, in_ falling for uv, rising for ov (10mv increments) -25 +25 mv threshold hysteresis v th_hys 0.5 %v th reset threshold tempco ? v th/c 50 ppm/ c max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc , in1 in4 = +2.7v to +5.5v; enable = margin = mr = abp = trken; t a = -40 c to +85 c, unless otherwise specified. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units tracking-differential-voltage hold ramp (note 3) v trk v out_ > v th_pl v out_ < v th_pg 95 125 155 mv tracking-differential-voltage hysteresis 25 mv tracking-differential fault voltage (note 3) v trk_f v out_ > v th_pl v out_ < v th_pg 200 250 300 mv 00 20 25 30 01 40 50 60 10 80 100 120 fault timeout period (note 4) t faultup , t faultdown register contents (table 16) 11 160 200 240 ms fault to gate delay t fg 2s in1 in4 input impedance r in1-4 for in_ voltages < the highest in_ supply 55 90 145 k ? out1 out4 input impedance r out1-4 out_ pulldown disabled 70 100 130 k ? power-on delay t po v abp v uvlo 3ms in_ to gate_ delay t d-gate in_ falling/rising, 100mv overdrive 6 s out_ rising, 100mv overdrive 3 ms out_ to pg_ delay t pok out_ falling, 100mv overdrive 25 s 000 25 s 001 10 12.5 15 010 20 25 30 011 40 50 60 100 80 100 120 101 160 200 240 110 320 400 480 gate, reset , autoretry timeout period (notes 5, 6) t reset, t auto, t gate register contents (table 16) 111 1280 1600 1920 ms 00 10 12.5 15 01 40 50 60 10 80 100 120 oc timeout period t oc register contents (table 16) 11 160 200 240 ms t a = 0 c to +85 c 560 800 1040 00 t a = -40 c to 0 c 480 800 1120 t a = 0 c to +85 c 280 400 520 01 t a = -40 c to 0 c 240 400 560 t a = 0 c to +85 c 140 200 260 10 t a = -40 c to 0 c 120 200 280 t a = 0 c to +85 c 70 100 130 track/sequence slew rate rising or falling trk slew register contents (table 16) 11 t a = -40 c to 0 c 60 100 140 v/s 00 96.25 97.5 98.75 01 93.75 95 96.25 10 91.25 92.5 93.75 in_ to out_ overcurrent threshold v th_oc register contents (table 16), out_ falling 11 88.75 90 91.25 % max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit 4 _______________________________________________________________________________________ electrical characteristics (continued) (v cc , in1 in4 = +2.7v to +5.5v; enable = margin = mr = abp = trken; t a = -40 c to +85 c, unless otherwise specified. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units 00 93.75 95 96.25 01 91.25 92.5 93.75 10 88.75 90 91.25 in_ to out_ power-good threshold v th_pg register contents (table 16), out_ rising 11 86.25 87.5 88.75 % v th_pg and v th_oc hysteresis v out_hys 0.5 % power low threshold v th_pl out_ falling 125 142 165 mv power low hysteresis v th_pl_hys 10 mv out_ to gnd pulldown impedance (when enabled) abp 2.5v 100 ? abp 2.5v, i sink = 4ma 0.3 rem output low v ol_rem abp 4.0v, i sink = 15ma 0.4 v abp 1.4v, i sink = 50a (pg_, reset only) 0.3 abp 2.5v, i sink = 1ma 0.3 output low pg1 pg4, hold , fault , oc , reset (note 2) v ol abp 4.0v, i sink = 4ma 0.4 v abp 1.4v, i sink = 50a 0.3 abp 2.5v, i sink = 1ma 0.3 gate1 gate4 output low v gol abp 4.0v, i sink = 4ma 0.8 v pg1 pg4, hold , fault , oc , reset , rem output open-drain leakage current i lkg output deasserted -1 +1 a gate_ output-voltage high v goh i gate_ = 0.5a in_ + 4.4 in_ + 5 in_ + 5.8 v gate_ pullup current i gateup during power-up/down, v gate_ = 1v 2.5 4.5 a gate_ pulldown current i gatedown during power-up/down, v gate_ = 4v 2.5 4.5 a v il 0.3 x abp margin , fault , hold , mr , enable input voltage v ih 0.6 x abp v mr input pulse width t mr 2s fault , hold , margin , mr, enable glitch rejection 100 ns digital input to logic delay, fault , hold , margin , mr , enable t d 1s margin , mr digital input to abp pullup resistance r p 70 100 130 k ? max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit _______________________________________________________________________________________ 5 electrical characteristics (continued) (v cc , in1 in4 = +2.7v to +5.5v; enable = margin = mr = abp = trken; t a = -40 c to +85 c, unless otherwise specified. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units trken input delay t en trken falling, 100mv overdrive 2 s input rising 1.245 1.285 1.320 trken reference voltage range v trken input falling 1.225 1.25 1.275 v trken input current i trken v trken = 1.25v -100 +100 na reference input voltage range v refin 1.225 1.25 1.275 v reference input resistance r refin v refin = 1.25v 500 k ? serial interface logic (sda, scl, a0, a1) logic-input low voltage v il 0.3 x abp v logic-input high voltage v ih 0.6 x abp v input leakage current i ilkg 1a output-voltage low v ol i sink = 3ma 0.4 v output leakage current i olkg 1a input/output capacitance c i/o 10 pf serial interface timing (sda, scl) serial clock frequency f scl 400 khz clock low period t low 1.3 s clock high period t high 0.6 s bus free time t buf 1.3 s start setup time t su:sta 0.6 s start hold time t hd:sta 0.6 s stop setup time t su:sto 0.6 s clock low to valid output t aa 0.1 0.9 s data out hold time t dh 50 ns data in setup time t su:dat 100 ns data in hold time t hd:dat 0ns scl/sda rise time t r 300 ns scl/sda fall time t f 300 ns transmit sda fall time t f c bus = 400pf 20 + 0.1 x c bus 300 ns scl/sda noise suppression time t i 50 ns byte write cycle time t wr 11 ms note 1: specifications guaranteed for the stated global conditions. 100% production tested at t a = +25 c and t a = +85 c. specifications at t a = -40 c are guaranteed by design. note 2: the internal supply voltage, measurable on abp, is equal to the maximum of in1 in4 and v cc supplies. note 3: differential between each of the out_ and the synch ramp voltage during power-up/down measured as v out_ - 2 x v synch . note 4: fault timeout starts to count at the beginning of each sequence of power-up/down and clears when the programmed out_ voltages track successfully. max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit 6 _______________________________________________________________________________________ timing diagrams in4 = 1.5v in3 = 1.8v in2 = 2.5v in1 = 3.3v v trken gnd gnd gnd gnd fault out4 = 1.5v out3 = 1.8v out2 = 2.5v out1 = 3.3v reset gnd bus voltage monitored through trken input v trken monitored through set thresholds on in_ inputs (eeprom-selectable) t gate max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit _______________________________________________________________________________________ 7 gnd gnd gnd gnd v trken v trken bus voltage monitored through trken input reset monitored through set thresholds on in_ inputs (eeprom-selectable) in4 = 1.5v in3 = 1.8v in2 = 2.5v in1 = 3.3v out4 = 1.5v out3 = 1.8v out2 = 2.5v out1 = 3.3v eeprom- adjusted slew rate t gate t gate t gate t gate t reset figure 2. sequencing timing diagram timing diagrams (continued) max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit 8 _______________________________________________________________________________________ enable synch out1 = 4v out2 = 3v out3 = 2v out4 = 1v figure 4. sequencing ramp down diagram full trk mix with 2 ramp full seq mix with 3 ramp (fast shutdown bit set) figure 5. mixed-mode tracking/sequencing examples timing diagrams (continued) gnd gnd gnd gnd t reset gate bus voltage monitored through trken input monitored through set thresholds on in_ inputs (eeprom-selectable) in1 = 2.5v in2 = 1.8v in4 = 0.7v in3 = 0.9v out1 = 2.5v out2 = 1.8v out3 = 0.9v out4 = 0.7v eeprom- selected slew rate eeprom- selected slew rate (forced into quick shutdown when in1 fails) v trken v trken reset figure 3. voltage tracking with forced shutdown (in1 uv failure) max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit _______________________________________________________________________________________ 9 typical operating characteristics (v cc = 3.3v, enable = margin = mr = abp = trken, t a = +25 c, unless otherwise noted.) 0.90 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 2.7 3.4 4.1 4.8 5.5 supply current vs. supply voltage max6876 toc01 supply voltage (v) supply current (ma) 1.100 1.050 1.000 0.950 0.900 -40 10 -15 35 60 85 normalized timeout period vs. temperature max6876 toc02 temperature ( c) normalized timeout period 0.975 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 -40 -15 10 35 60 85 normalized in_ threshold vs. temperature max6876 toc03 temperature ( c) normalized in_ maximum in_ transient duration vs. in_ threshold overdrive max6876 toc04 in_ threshold overdrive (mv) maximum in_ transient duration ( s) 100 10 10 20 30 40 50 60 70 80 90 100 110 120 130 0 1 1000 0 1.0 0.5 2.5 2.0 1.5 3.0 3.5 4.5 4.0 5.0 069 3 1215182124273033 gate output-voltage low vs. sink current max6876 toc05 i sink (ma) v gol (v) 0.985 0.990 1.000 0.995 1.005 1.010 -40 10 -15 35 60 85 normalized pg and oc threshold vs. temperature max6876 toc06 temperature ( c) normalized pg and oc 10ms/div tracking mode out_ 0v max6876 toc07 out4 out3 out2 out1 1v/div 20ms/div tracking mode with fast shutdown out_ 0v max6876 toc08 out4 out3 out2 out1 1v/div 10ms/div sequencing mode out_ 0v max6876 toc09 out4 out3 out2 out1 1v/div max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit 10 ______________________________________________________________________________________ pin description pin name function 1v cc optional supply voltage input. connect v cc to an alternate (i.e., always-on) supply if desired. v cc supports operation/communication when the monitored supplies are not powered or are below the minimum required operating voltage. in a master/slave application, connect all v cc pins to a common supply line. 2 gnd ground 3 abp internal analog bypass. bypass abp with a 1f capacitor to gnd. abp maintains the device supply voltage during rapid power-down conditions. 4 trken tracking enable input. trken must be higher than 1.285v to enable voltage tracking power-up operation. when trken falls below 1.25v (3% hysteresis), out_ tracks down. connect trken to an external resistor-divider network to set the desired monitor threshold. connect trken to abp if not used. 5 synch selectable tracking synchronization output/input. synch allows multiple max6876 devices to control tracking of multiple power supplies (up to 16 voltages on the same i 2 c bus). one device is programmed as synch master and all other devices are programmed as slaves. synch on the master outputs the common ramp voltage to which all out_ voltages are tracked (with active control loops). synch of the slave devices is input for the ramp control voltage (no internal ramp is generated in the slaves) (see the synch section). connect synch to other synch pins only. 6 hold active-low, open-drain synchronization hold output/input. hold communicates synchronization status between master/slave devices in multiple max6876 applications. the hold output remains asserted while selected tracking in_ inputs are below their selected thresholds (the slave device can delay tracking start until its inputs are at their required stable voltage levels) or held low by the master when it is counting the autoretry time after a detected fault condition (see the synchronization hold output ( hold ) section). slave device synch are inputs for the ramp control voltage. typical operating characteristics (continued) (v cc = 3.3v, enable = margin = mr = abp = trken, t a = +25 c, unless otherwise noted.) 20ms/div out_ 0v max6876 toc10 1v/div out4 out3 out2 out1 mixed mode 20ms/div out_ 0v max6876 toc11 1v/div out4 out3 out2 out1 mixed mode with fast shutdown max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit ______________________________________________________________________________________ 11 pin description (continued) pin name function 7 oc active-low, open-drain overcurrent output. oc asserts low if any monitored in_ to out_ voltage falls out of the selected percentage of the in_ voltage range (v th_oc ) for more than the programmed t oc. oc monitoring begins only after supply tracking or sequencing has been completed and is disabled during power-down operation. 8 rem open-drain bus removal output. rem signals when it is safe to remove the card after a controlled track/sequence-down operation. rem goes high impedance when all v out_ < v th_pl . rem requires an external pullup resistor. in master/slave mode, rem can be ored together (the common rem connection remains low if any v out_ > v th_pl threshold) ( see the typical application circuit and the bus removal output (rem) section). 9 fault active-low, open-drain tracking fault alert output or input. fault asserts low if a tracking failure is present for longer than the specified fault period or if tracking voltages fails by more than 250mv (see the fault section). 10 reset active-low, open-drain reset or power-good output. reset is low during power-up and power- down tracking. reset goes high after all selected out_ outputs exceed their selected thresholds and the reset timeout period t reset has expired. the reset timeout period is internally selectable. reset requires an external pullup resistor. 11 enable logic enable input. enable must be high to enable voltage tracking/sequencing power-up operation. out_ begins tracking down when enable is low. connect to abp if not used. 12 margin active-low margin input. the margin function allows systems to be tested with supply voltages outside their normal ranges without affecting supply tracking/sequencing or reset states. margin functionality is usually enabled after systems have powered up in normal mode. the margin functionality is disabled (returns to normal monitoring mode) after margin returns high. margin is internally pulled up to abp through a 100k ? resistor. 13, 23 n.c. no connection. not internally connected. 14 mr active-low manual reset input. when mr is low, reset goes low and remains asserted for the selected timeout period after mr is pulled high. mr is internally pulled up to abp through a 100k ? resistor. 15 sda serial-interface data input/output (open-drain). sda requires an external pullup resistor. 16 scl serial-interface clock input. scl requires an external pullup resistor. 17 a0 18 a1 serial-interface address inputs. the inputs allow up to four max6876 devices to be addressed when sharing a common data bus. a1 and a0 should be connected to gnd or abp. 19 pg1 20 pg2 21 pg3 22 pg4 power-good output, open-drain. each pg_ output signals when its monitored out_ voltage is within the selected percentage of the in_ voltage range (v th_pg ). pg_ is low until out_ exceeds the programmable threshold (v th_pg ) for more than t pok . pg_ outputs are open-drain and require external pullups if used. max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit 12 ______________________________________________________________________________________ pin description (continued) pin name function 24 refin reference voltage input. the max6876 can be configured to use the internal 1.25v reference or an external voltage reference. refin is tri-stated when using the internal reference. refin provides the threshold voltage for the voltage detectors when using an external voltage reference. use an external voltage reference when tighter voltage-detector accuracy is desired. when configured to an internal reference, leave refin unconnected. when configured for an external reference, connect a 1.225v to 1.275v reference to refin. 25 out4 monitored output voltage. the out4 output is monitored to control the supply slew rate and tracking performance. out1 out4 begin to track up after the internal supply (abp) exceeds the minimum voltage requirements, v trken > 1.285v threshold, enable is logic high, and in1 in4 are all within their selected thresholds. the out4 output falls out of the tracking equation as out4 approaches in4; other out_ supplies continue tracking up without signaling a system fault. out_ outputs are tracked down during power-off conditions. 26 gate4 gate drive for external n-channel fets. gate4 begins enhancing the external n-channel fets when all monitored inputs are within their selected thresholds (0.5v to 5.5v), at least one in_ input or v cc is above the minimum operating voltage, v trken > 1.285v threshold, and the enable input is logic high. during power-up mode, gate_ voltages are enhanced with internal control loops forcing all out_ voltages to track the reference ramp (synch) at a programmed slew rate. an internal charge pump boosts gate4 to v in4 + 5v to fully enhance the external n-channel fet when power-up is complete. 27 in4 supply voltage and tracked input voltage. nominal supply range is 0.5v to 5v. in1, in2, in3, in4, or v cc must be greater than the internal uvlo (v abp = 2.7v) to enable the tracking functionality. the in4 input is monitored with internally selected thresholds to ensure all supplies have stabilized before tracking (or sequencing) is enabled. 28 out3 monitored output voltage. out3 is monitored to control the supply slew rate and tracking performance. out1 out4 begin to track up after the internal supply (abp) exceeds the minimum voltage requirements, v trken > 1.285v threshold, enable is logic high, and in1 in4 are all within their selected thresholds. the out3 output falls out of the tracking equation as out3 approaches in3; other out_ supplies continue tracking up without signaling a system fault. out_ outputs are tracked down during power-off conditions. 29 gate3 gate drive for external n-channel fets. gate3 begins enhancing the external n-channel fets when all monitored inputs are within their selected thresholds (0.5v to 5.5v), at least one in_ input or v cc is above the minimum operating voltage, v trken > 1.285v threshold, and the enable input is logic high. during power-up mode, gate_ voltages are enhanced with internal control loops forcing all out_ voltages to track the reference ramp (synch) at a programmed slew rate. an internal charge pump boosts gate3 to v in3 + 5v to fully enhance the external n-channel fet when power-up is complete. 30 in3 supply voltage and tracked input voltage. nominal supply range is 0.5v to 5v. in1, in2, in3, in4, or v cc must be greater than the internal uvlo (v abp = 2.7v) to enable the tracking functionality. in3 is monitored with internally selected thresholds to ensure all supplies have stabilized before tracking (or sequencing) is enabled. 31 out2 monitored output voltage. out2 is monitored to control the supply slew rate and tracking performance. out1 out4 begin to track up after the internal supply (abp) exceeds the minimum voltage requirements, v trken > 1.285v threshold, enable is logic high, and in1 in4 are all within their selected thresholds. out2 output falls out of the tracking equation as out2 approaches in2; other out_ supplies continue tracking up without signaling a system fault. out_ outputs are tracked down during power-off conditions. max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit ______________________________________________________________________________________ 13 pin description (continued) pin name function 32 gate2 gate drive for external n-channel fets. gate2 begins enhancing the external n-channel fets when all monitored inputs are within their selected thresholds (0.5v to 5.5v), at least one in_ input or v cc is above the minimum operating voltage, v trken > 1.285v threshold, and the enable input is logic high. during power-up mode, gate_ voltages are enhanced with internal control loops forcing all out_ voltages to track the reference ramp (synch) at a programmed slew rate. an internal charge pump boosts gate2 to v in2 + 5v to fully enhance the external n-channel fet when power-up is complete. 33 in2 supply voltage and tracked input voltage. nominal supply range is 0.5v to 5v. in1, in2, in3, in4, or v cc must be greater than the internal uvlo (v abp = 2.7v) to enable the tracking functionality. in2 is monitored with internally selected thresholds to ensure all supplies have stabilized before tracking (or sequencing) is enabled. 34 out1 monitored output voltage. each out1 is monitored to control the supply slew rate and tracking performance. out1 out4 begin to track up after the internal supply (abp) exceeds the minimum voltage requirements, v trken > 1.285v threshold, enable is logic high, and in1 in4 are all within their selected thresholds. the out1 output falls out of the tracking equation as out1 approaches in1; other out_ supplies continue tracking up without signaling a system fault. out_ outputs are tracked down during power-off conditions. 35 gate1 gate drive for external n-channel fets. gate1 begins enhancing the external n-channel fets when all monitored inputs are within their selected thresholds (0.5v to 5.5v), at least one in_ input or v cc is above the minimum operating voltage, v trken > 1.285v threshold, and the enable input is logic high. during power-up mode, gate_ voltages are enhanced with internal control loops forcing all out_ voltages to track the reference ramp (synch) at a programmed slew rate. an internal charge pump boosts gate1 to v in1 + 5v to fully enhance the external n-channel fet when power-up is complete. 36 in1 supply voltage and tracked input voltage. nominal supply range is 0.5v to 5v. in1, in2, in3, in4, or v cc must be greater than the internal uvlo (v abp = 2.7v) to enable the tracking functionality. in1 is monitored with internally selected thresholds to ensure all supplies have stabilized before tracking (or sequencing) is enabled. ep exposed paddle. exposed paddle is internally connected to gnd. detailed description the max6876 eeprom-configurable, multivoltage power tracker/supervisor monitors four system voltages and ensures proper power-up and power-down condi- tions for systems requiring voltage tracking and/or sequencing. the max6876 provides a highly config- urable solution as key thresholds and timing parame- ters are programmed through an i 2 c interface and these values are stored in internal eeprom. in addition to tracking and sequencing voltages, the max6876 also provides supervisory functions as well as an over- current detection circuit. the max6876 features programmable undervoltage and overvoltage thresholds for each input supply. the thresholds are eeprom configured in 10mv (0.5v to 3.05v) or 20mv (1.0v to 5.5v) increments. when all of the voltages are within their specifications, the device turns on the external n-channel mosfets to either sequence or track the voltages to the system. all of the voltages can be sequenced or tracked or powered up with a combination of the two options. during voltage tracking, the voltage at the gate of each mosfet is increased to slowly turn on each out_. the gate delay is eeprom-selectable from 25s to 1.6s. the max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit 14 ______________________________________________________________________________________ voltages at the sources of the mosfets are compared to each other to ensure that the voltage differential between each monitored supply does not exceed 250mv (typ). tracking is dynamically adjusted to force all outputs to track within a 125mv window from a ref- erence ramp; if, for any reason, any supply fails to track within 250mv from the reference ramp, the fault output is asserted, the power-up mode is terminated, and all outputs are powered off. power-up mode is in the same way terminated if the controlled voltages fail to complete the ramp up within a programmable fault timeout. the max6876 generates all required voltages (with internal charge pumps) and timing to control up to four external n-channel mosfets for the out1 out4 supply voltages. a synchronization feature allows up to 16 voltages to be tracked simultaneously. in addition, hold and synch communicate synchronization status between master/slave devices in multiple max6876 applications. other features of the max6876 include a reset circuit with an i 2 c-programmable timeout feature. a manual reset input ( mr ) and a margin disable input ( margin ) allow for more control during the manufacturing process. the device also features four power-good outputs (pg_), an overcurrent output ( oc ), and a bus-removal safe (rem) output. the device has an accurate internal 1.25v reference; for greater accuracy, connect an external +1.25v reference to refin. comp comp comp comp control logic enable trken mr margin 1.25v internal supply/uvlo eeprom/ configuration registers ref refin a1 a0 scl sda gnd in1 uv/ov in2 uv/ov in3 uv/ov in4 uv/ov rem oc fault reset synch hold tracking monitors out1 out2 out3 out4 in1 in2 in3 in4 ramp generator in1 in2 in3 in4 v cc charge pump over- current detect v cp1 = v in1 + 5v comp in1 in1 v thpg in2 to out2 control block gate2 pg2 out2 in3 to out3 control block gate3 pg3 out3 in4 to out4 control block gate4 pg4 out4 pg1 max6876 ramp abp gnd abp gate1 out1 abp functional diagram max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit ______________________________________________________________________________________ 15 modes of operation the max6876 provides three different modes of opera- tion: tracking, sequencing, and mixed modes. the mixed mode is a combination of both tracking and sequencing modes (see the mixed mode (tracking/ sequencing) section). tracking when all selected inputs exceed their selected thresh- olds, v trken > 1.285v, and enable is logic high, the tracking process is initialized. the max6876 generates an internal ramp voltage that drives the control loops for the desired tracked voltage. the tracking functional- ity is monitored with a comparator control block (see the functional diagram and figure 5). the comparators monitor and control each output voltage with respect to the common tracking ramp voltage to stay within a 125mv differential window, monitor each tracked out- put voltage with respect to its input voltage, and moni- tor each output voltage with respect to gnd during power-up/retry cycles. under normal conditions each out_ voltage will track the ramp voltage until the out_ voltage approximates the in_ voltage (the external n-channel fet is saturated). the slew rate for the ramp voltage is selected through eeprom. master/slave operation (tracking only) to support voltage tracking for more than four supplies, combine multiple max6876 devices. two max6876 devices (one master/one slave) track up to eight supply voltages and four max6876 devices (one master and three slaves) track up to 16 supply voltages. each device must be programmed to act in master or slave mode (only one master is allowed); the default state is single device (see table 1). the max6876 outputs the ramp control voltage with the synch output when con- figured as a master device. this ramp allows multiple devices to synchronize with the master when slave synchs are configured as inputs. for proper function- ality control, connect all enable pins together. in mas- ter/slave mode, all controlled supplies are tracked up/down (no mixed sequencing/tracking modes are supported). in master-slave application, the part is intended to provide only tracking for the four supplies (only one ramp is generated). to control one particular channel, insert a 1 in any of the four possible posi- tions (one row for each channel contains 4 bits) and the circuit will generate the proper signals (see figure 6). for multiple max6876 operations, the ramp control volt- age is brought out of the master s synch (programmed as an output) and into the slave s synch (programmed as an input). the highest tracked supply must be con- nected to one of the master s in_ inputs. when all in_ threshold conditions are met (on master and slaves), the master ramp begins rising at the selected ramp slew rate. during normal operation all out_ voltages (for master and slave) track the ramp voltage. if the slave s out_ voltages do not properly follow the ramp voltage (exceed 125mv differential), the slave device asserts hold low. the master recognizes the hold and holds the ramp voltage, allowing the slave s slower out_ voltages to register address eeprom memory address bit range description if 00, the device configuration is a single device. if 01, the device configuration is multiple devices, slave. if 10, the device configuration is multiple devices, slave. 09h 29h [7:6] if 11, the device configuration is multiple devices, master. table 1. master/slave settings r0bh[7:0] r0ch[7:0] ramp 1 ramp 2 ramp 3 ramp 4 bit 0 bit 4 bit 0 bit 4 out1 bit 1 bit 5 bit 1 bit 5 out2 bit 2 bit 6 bit 2 bit 6 out3 bit 3 bit 7 (msb) bit 3 bit 7 (msb) out4 figure 6. mapping tracking and sequencing modes max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit 16 ______________________________________________________________________________________ catch up. when the slave s voltages approach the ramp voltage, the slave releases hold and the master allows the ramp voltage to begin rising again. all tracking must be completed by the selected tracking fault timeout peri- od or the supplies are powered down. the slave hold output is asserted low until the selected tracking in_ volt- ages are within their selected thresholds. this ensures that the master does not begin the tracking operation until the slave s input voltages (in_) have properly stabilized. sequencing the sequencing operation can be initialized by proper- ly setting the bit of registers 0bh and 0ch. during a sequencing power-up phase, each out_ is indepen- dently powered on with a controlled slew rate. no more than one supply is powered on for each generated ramp. the bits of registers 0bh and 0ch establish the turn-on order. during each phase, the ramp is enabled to start only after the t gate timeout has been counted. the sequencing phase will be considered complete when all the channels programmed to power on reach the independently set pg_ thresholds (see figure 5). mixed mode (tracking/sequencing) the max6876 is fully programmable to generate up to four ramps during power-up or power-down modes. each out_ voltage independently is programmed to follow any of the control ramps generated by the max6876. to do the latter, set the bits on register 0bh and 0ch to 1 for each channel. the following are pro- gramming examples of different power-up modes ( = sequence, / = track): 0bh = 0000 1111 0ch = 0000 0000 tracking mode: out1/out2/out3/out4 on ramp1 0bh = 1000 0100 0ch = 0010 0001 sequencing mode: out3 out4 out1 out2 on ramp1, ramp2, ramp3, ramp4 0bh = 1100 0001 0ch = 0010 0000 mix mode*: out1 out4/out3 out2 on ramp1, ramp2, ramp4 *(ramp3 is not considered because no out_ outputs are selected by bit [0:3] of 0ch.) drive enable or trken low or use a software com- mand to initiate a controlled power-down. the max6876 powers down the out_ voltages in a reverse sequence from the one at power-up when this option is selected. for example, with the following power-up sequence: out1 out4/out3 out2 then the power-down sequence will be: out2 out4/out3 out1 configuring tracking and sequencing modes to configure tracking and sequencing modes, insert 1 and 0 into the 0bh and 0ch registers (see table 2). figure 6 shows how to map for tracking and sequencing modes. each out_ output can follow one of the four possible ramps in tracking or sequencing mode (16 bits are available) and one bit set to 1, means that the channel of the interested row is pow- ered up/down by the corresponding ramp (see figure 6). 1) if the depicted table (in figure 6) is made by all 1s, the part simply generates a single ramp (all channels in tracking mode since the first column is full of 1s, ) and it ignores the remaining values of the other 12 bits. 2) if one row contains more than one symbol 1, only the first encountered (columns starting with r0bh [3:0]) is taken into account and the channel is pow- ered up/down with the corresponding ramp. 3) if there is one (or more) row in which all 4 bits are set to 0, it means that the device will not control that particular channel. 4) if there is one (or more) column where all 4 bits are set to 0, the device skips that ramp and its associ- ate t d-gate. in master-slave applications, the device is intended to provide only tracking for the four supplies (only one ramp can be generated). to control one particular channel, only insert a 1 in any of the four possible positions (one row for each channel contains 4 bits) and the device generates the proper signals. when three or less ramps are needed, use consecutive ramps starting with ramp 1. power-down and power-up when all the in_ inputs are within the selected threshold range and the internal enable is logic high (figure 7), the device initiates a power-up phase. during power-up, the out_ outputs are forced by an internal loop that controls the gate_ of the external mosfet to follow the reference ramp voltage. this phase for each individual ramp must be completed within the programmable fault timeout time; otherwise, the part will force a shutdown on the gate_. once the power-up is completed, a power-down phase can be initiated by forcing the internal enable low. two power-down options are available: a fast-shutdown option where all gate_ gates are quickly turned off or a reverse- order option. this reverse-order option allows the out_ voltage to be powered down with a controlled slew rate and in the reverse order they have been powered up (see figure 2). max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit ______________________________________________________________________________________ 17 to speed up the discharge of the out_ voltage, an optional 100 ? pulldown resistor can be selected (see table 3). slew-rate control the reference ramp voltage slew rate during any con- trolled power-up/down phase can be programmed in the 100v/s to 800v/s range. before any power-up or retry cycle, the max6876 must first ensure that all out_ voltages are near ground (below the v th_pl power low threshold). an internal programmable track- ing timeout period can be selected to signal a fault and shut down the output voltages if tracking takes too long (see table 4). power-supply tracking operation should be completed within the selected fault timeout period. for selected control ramps of 100v/s the normal tracking time should be approximately 50ms (5v supply, sr = 100v/s). the total tracking time is extended when the max6876 must vary the control slew rate to allow slow supplies to catch up. if the external fet is too small (rds is too high for the selected load current and in_ source current), the out_ voltage may never reach the control ramp voltage. autoretry and latch-off functions the max6876 features latch-off or autoretry mode to power on again after a fault condition has been detect- ed. toggle enable, i 2 c command bit, and trken or cycle device power to clear the latch. set bit 5 of regis- ter 09h to 1 to program the max6876 in latch-off mode, or 0 to program for autoretry mode. the autoretry time can be programmed with bits 2, 3, and 4 of register 09h (see table 5). during autoretry, the gate drive remains off and fault remains asserted. in a master-slave application, fault is asserted low until all the out_ outputs of each device are discharged to gnd, and only the master counts the autoretry time while hold remains low (see table 5). stability comment no external compensation is required for tracking or slew-rate control. powering the max6876 the max6876 derives power from v cc or the voltage- detector inputs: in1 in4 (see the functional diagram ). v cc (if being used) or one of the in_ inputs must be at least +2.7v to ensure full device operation. the highest input voltage on in1 in4 or v cc supplies power to the device. internal hysteresis ensures that the supply input that initially powers the device contin- ues to power the device when multiple input voltages are within 50mv (typ) of each other. register address eeprom memory address bit range description bit 7 if 1, out4 on ramp 2 bit 6 if 1, out3 on ramp 2 bit 5 if 1, out2 on ramp 2 bit 4 if 1, out1 on ramp 2 bit 3 if 1, out4 on ramp 1 bit 2 if 1, out3 on ramp 1 bit 1 if 1, out2 on ramp 1 0bh 2bh [7:0] bit 0 if 1, out1 on ramp 1 bit 7 if 1, out4 on ramp 4 bit 6 if 1, out3 on ramp 4 bit 5 if 1, out2 on ramp 4 bit 4 if 1, out1 on ramp 4 bit 3 if 1, out4 on ramp 3 bit 2 if 1, out3 on ramp 3 bit 1 if 1, out2 on ramp 3 0ch 2ch [7:0] bit 0 if 1, out1 on ramp 3 table 2. configuring tracking and sequencing modes max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit 18 ______________________________________________________________________________________ inputs in1?n4 the in1 in4 voltage detectors monitor voltages from 1v to 5.5v in 20mv increments, or +0.5v to +3.05v in 10mv increments. use the following equations to set the threshold voltages for in_: for +1v to +5.5v range. for +0.5v to +3.05v range. where v th is the desired threshold voltage and x is the decimal code for the desired threshold (table 6). for the +1v to +5.5v range, x must equal 225 or less; oth- erwise, the threshold exceeds the maximum operating voltage of in1 in4 (table 6). an overvoltage or under- voltage failure on an in_ input immediately shuts down all the out_ outputs and generates a fault in the master/slave condition. x vv v th = -.5 0 001 . x vv v th = -1 002 . register address eeprom memory address bit range description bit 7 if 1, reverse order of track/sequence power-down if 0, gate_ fast pulldown bit 6 if 1, out1 charges with internal pulldown if 0, no pulldown is allowed bit 5 if 1, out2 charges with internal pulldown if 0, no pulldown is allowed bit 4 if 1, out3 charges with internal pulldown if 0, no pulldown is allowed 13h 33h [7:3] bit 3 if 1, out4 charges with internal pulldown if 0, no pulldown is allowed 00 fault power-up timer value = 25ms 01 fault power-up timer value = 50ms 10 fault power-up timer value = 100ms [7:6] 11 fault power-up timer value = 200ms 00 fault power-down timer value = 25ms 01 fault power-down timer value = 50ms 10 fault power-down timer value = 100ms 0ah 2ah [5:4] 11 fault power-down timer value = 200ms table 3. program power-down and power-up register address eeprom memory address bit range description 00 track/sequence slew rate (rise or fall) = 800v/s 01 track/sequence slew rate (rise or fall) = 400v/s 10 track/sequence slew rate (rise or fall) = 200v/s 12h 32h bit [7:6] 11 track/sequence slew rate (rise or fall) = 100v/s table 4. setting the slew rate max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit ______________________________________________________________________________________ 19 register address eeprom memory address bit range description 5 if 1, latch-on fault if 0, autoretry 000 autoretry timer value = 25s 001 autoretry timer value = 12.5ms 010 autoretry timer value = 25.0ms 011 autoretry timer value = 50.0ms 100 autoretry timer value = 100.0ms 101 autoretry timer value = 200.0ms 110 autoretry timer value = 400.0ms 09h 29h [4:2] 111 autoretry timer value = 1600.0ms table 5. program autoretry/latch off register address eeprom memory address bit range description 00h 20h [7:0] in1 undervoltage threshold v th = 1.0 + n x 20mv (if r08[7] = 0) v th = 0.5 + n x 10mv (if r08[7] = 1) where n is the register content decimal representation. note that v th ranges must be 1v to 5.5v and 0.5v to 3.05v, respectively. 01h 21h [7:0] in2 undervoltage threshold v th = 1.0 + n x 20mv (if r08[6] = 0) v th = 0.5 + n x 10mv (if r08[6] = 1) where n is the register content decimal representation. note that v th ranges must be 1v to 5.5v and 0.5v to 3.05v, respectively. 02h 22h [7:0] in3 undervoltage threshold v th = 1.0 + n x 20mv (if r08[5] = 0) v th = 0.5 + n x 10mv (if r08[5] = 1) where n is the register content decimal representation. note that v th ranges must be 1v to 5.5v and 0.5v to 3.05v, respectively. 03h 23h [7:0] in4 undervoltage threshold v th = 1.0 + n x 20mv (if r08[4] = 0) v th = 0.5 + n x 10mv (if r08[4] = 1) where n is the register content decimal representation. note that v th ranges must be 1v to 5.5v and 0.5v to 3.05v, respectively. 04h 24h [7:0] in1 overvoltage threshold v th = 1.0 + n x 20mv (if r08[7] = 0) v th = 0.5 + n x 10mv (if r08[7] = 1) where n is the register content decimal representation. note that v th ranges must be 1v to 5.5v and 0.5v to 3.05v, respectively. table 6. in1 in4 threshold settings max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit 20 ______________________________________________________________________________________ manual reset input ( mr ) the manual reset ( mr ) input initiates a reset condition. mr is internally pulled up to abp through a 100k ? resistor. when mr is low, reset remains low for the selected reset timeout period after mr transitions from low to high (see the reset output ( reset ) section). margin input ( margin ) margin allows system-level testing while power sup- plies exceed the normal ranges. drive margin low before varying system voltages below/above the select- ed threshold without signaling an error. margin makes it possible to vary the supplies without a need to repro- gram the in_ or pg_ thresholds and prevents tracker/sequencer alerts or faults. drive margin high or leave it floating for normal operating mode. enable drive logic enable input high to initiate voltage track- ing/sequencing during power-up operation. drive logic enable low to initiate tracking/sequencing power-down operation. when enable is not used, connect to abp. when the max6876 is configured to use the i 2 c on/off command, a valid i 2 c signal must be received before the device begins the power-up tracking/sequencing routine. the internal enable logic is an and function of the enable logic, the trken logic, and the i 2 c con- trol/command logic (figure 7). when all three and gate input variables are true (and the monitored in/out volt- ages meet their required thresholds), turn-on is allowed. when any and input variable becomes false, the turn- off cycle (track/sequence down) begins immediately. drive enable and trken high if only the i 2 c com- mand is to be used to turn on/off the device. the detec- tors monitoring in_ and out_ voltages, and overcurrent conditions have a higher priority after a power-on routine has been initiated by the internal enable logic. if a fault occurs during the power-up cycle, the device is powered down immediately, inde- pendent of enable, trken, and the i 2 c shutdown register address eeprom memory address bit range description 05h 25h [7:0] in2 overvoltage threshold v th = 1.0 + n x 20mv (if r08[6] = 0) v th = 0.5 + n x 10mv (if r08[6] = 1) where n is the register content decimal representation. note that v th ranges must be 1v to 5.5v and 0.5v to 3.05v, respectively. 06h 26h [7:0] in3 overvoltage threshold v th = 1.0 + n x 20mv (if r08[5] = 0) v th = 0.5 + n x 10mv (if r08[5] = 1) where n is the register content decimal representation. note that v th ranges must be 1v to 5.5v and 0.5v to 3.05v, respectively. 07h 27h [7:0] in4 overvoltage threshold v th = 1.0 + n x 20mv (if r08[4] = 0) v th = 0.5 + n x 10mv (if r08[4] = 1) where n is the register content decimal representation. note that v th ranges must be 1v to 5.5v and 0.5v to 3.05v, respectively. bit 7 if 0, 20mv steps in v th setting for in1 if 1, 10mv steps in v th setting for in1 bit 6 if 0, 20mv steps in v th setting for in2 if 1, 10mv steps in v th setting for in2 bit 5 if 0, 20mv steps in v th setting for in3 if 1, 10mv steps in v th setting for in3 08h 28h [7:4] bit 4 if 0, 20mv steps in v th setting for in4 if 1, 10mv steps in v th setting for in4 table 6. in1 in4 threshold settings (continued) max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit ______________________________________________________________________________________ 21 command (table 7). if a latch-on fault mode is chosen, a toggle on the internal enable clears the latch condi- tion and restarts the device after a fault condition (figure 7). reference voltage input (refin) the max6876 features an internal +1.25v voltage refer- ence. the voltage reference sets the threshold of the voltage detectors. leave refin unconnected when using the internal reference. refin accepts an external reference in the +1.225v to +1.275v range. use table 8 commands to select the external reference. track enable input (trken) the track enable (trken) monitor input is another fea- ture of the max6876. to enable voltage-tracking power-up operation, drive trken higher than 1.285v. when trken goes below 1.25v, out_ outputs start tracking down. connect trken to an external resistor- divider network to set the desired monitor threshold. connect trken to abp if not used. synch the max6876 provides selectable tracking synchro- nization output or input (synch). synch allows track- ing of up to 16 power supplies on the same i 2 c bus. one device is programmed as the synch master and the other devices are programmed as slaves. synch of the master device outputs the common ramp voltage to which all out_ voltages are tracked. the synch pins of the slave devices are inputs for the ramp control voltage (no internal ramp is generated in the slave devices) (see table 1). monitored outputs out1?ut4 the max6876 monitors four out_ outputs to control the tracking/sequencing performance. after the internal supply (abp) exceeds the minimum voltage (2.7v) requirements, trken > 1.25v, the internal enable input is logic high, and in1 in4 are all within their selected thresholds, out1 out4 will begin to track or sequence. during power-up mode, the max6876 drives the gates of the external n-channel fets to force the out_ volt- ages to track the internally set ramp voltage. if out_ voltages vary from the ramp voltage by more than 125mv, an internal comparator signals an alert that dynamically adjusts the ramp voltage (stops the ramp until the slow out_ catches up). during power-down mode, an internal pulldown resistor (100 ? ) on out_ can be enabled to help discharge load capacitance. register address eeprom memory address bit range description bit 1 if 1, check enable with i 2 c enable control bit if 0, ignore enable with i 2 c 09h 29h [1:0] bit 0 if 0, enable with i 2 c = 0, i 2 c enable command bit if 1, enable with i 2 c = 1 table 7. program enable register address eeprom memory address bit range description 11h 31h 0 bit 0 if 1, selects external reference; 0 selects internal reference table 8. select external reference enable internal enable trken i 2 c enable control bit (ram register) 1 = yes 0 = no i 2 c enable command bit (ram register) 0 = off 1 = on 09h[0] 09h[1] v trken figure 7. logic enable max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit 22 ______________________________________________________________________________________ outputs gate_ the max6876 features four gate_ outputs to drive four external n-channel fet gates. the following conditions must be met before gate_ begins enhancing the external n-channel fet_: 1) all monitored inputs (in1 in4) are above their selected thresholds (0.5v to 5.5v) 2) at least one in_ input or v cc is above 2.7v 3) drive enable high 4) trken > 1.25v at power-up mode, gate_ voltages are enhanced con- trol loops so all out_ voltages track together at a user- selected slew rate. each gate_ is internally pulled up to 5v above its relative in_ voltage to fully enhance the external n-channel fet when power-up is complete. in sequencing/tracking mode, a gate delay timeout is internally counted prior to the start of each control ramp (see figures 1 and 2 and table 9). fault the max6876 offers an open-drain, active-low tracking fault alarm ( fault ). fault asserts low when a power- up phase is not completed within the specified fault period or if tracking voltages fail by more than 250mv. for multiple max6876 applications, fault is an input/output pin and communicates fault information between master/slave devices. connect all fault pins in an ored configuration to force simultaneous shut- down on all max6876s (table 10.) see the typical application circuit . power-good outputs (pg_) the max6876 features four power-good (pg_) outputs. pg_ outputs are open-drain and require external pullups. when the out_ output is within the selected percent- age of the in_ voltage range (v th_pg ), the correspond- ing pg_ output goes high impedance. pg_ stays low until the out_ voltage exceeds the programmable v th_pg threshold for more than t pok (table 11). register address eeprom memory address bit range description 000 gate-delay timer value = 25s 001 gate-delay timer value = 12.5ms 010 gate-delay timer value = 25.0ms 011 gate-delay timer value = 50.0ms 100 gate-delay timer value = 100.0ms 101 gate-delay timer value = 200.0ms 110 gate-delay timer value = 400.0ms 0fh 2fh [7:5] 111 gate-delay timer value = 1600.0ms table 9. gate-delay time settings register address eeprom memory address bit range description [7:6] bit [7:6] 00 fault power-up timer value = 25ms 01 fault power-up timer value = 50ms 10 fault power-up timer value = 100ms 11 fault power-up timer value = 200ms 0ah 2ah [5:4] bit [5:4] 00 fault power-down timer value = 25ms 01 fault power-down timer value = 50ms 10 fault power-down timer value = 100ms 11 fault power-down timer value = 200ms table 10. fault power-up and power-down time settings max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit ______________________________________________________________________________________ 23 bus removal output (rem) the max6876 features an open-drain bus removal (rem) output. rem signals when it is safe to remove the card after a controlled track/sequence power-down operation. to initiate a power-down, drive enable low or send an i 2 c power-down command. rem monitors out_ and when any of the out_ voltages are above the v th_pl threshold, rem stays low. when all out_ outputs are below v th_pl , rem goes high impedance. connect rem to an external pullup resistor/led chain to visually signal when it is safe to remove a powered board from the bus. in tracking mode when rem is used in master/slave operations, connect all rem pins together. the com- mon rem connection remains low if any out_ supply is above the v th_pl threshold. overcurrent output ( oc ) the open-drain, active-low oc output asserts low if an overcurrent condition is detected in any selected channel for longer than t oc . overcurrent conditions are deter- mined as a differential voltage between in_ and out_. oc monitoring begins only after supply tracking or sequencing has been completed and is disabled during power-down operation (table 12). reset output ( reset ) the reset output, reset, is an open-drain output that monitors the selected out_ voltages. the selected out_ voltages must exceed their selected pg_ thresh- olds for the selected reset timeout period (t rp ) before reset is deasserted. a manual reset input ( mr ) can assert reset . reset remains low while mr is low. reset remains low for the selected reset timeout peri- od (t rp ) after mr transitions from low to high (table 13). synchronization hold output ( hold ) the max6876 features an open-drain, active-low syn- chronization alert output/input. hold communicates synchronization status between master/slave devices in multiple max6876 applications. when a slave device detects a tracking problem with respect to the master synch signal, the slave asserts hold low. when tracking is back under control, the slave s hold is deasserted and goes high again. the hold output remains asserted while selected tracking in_ inputs are below their selected thresholds (the slave device can delay a tracking start until its inputs are at their required stable voltage levels) or held low by the master when it is counting the autoretry time after a detected fault con- dition. connect hold pins only to other max6876 hold pins. register address eeprom memory address bit range description 00 in4 to out4 power-good threshold = 95% 01 in4 to out4 power-good threshold = 92.5% 10 in4 to out4 power-good threshold = 90% [7:6] 11 in4 to out4 power-good threshold = 87.5% 00 in3 to out3 power-good threshold = 95% "01" in3 to out3 power-good threshold = 92.5% 10 in3 to out3 power-good threshold = 90% 11 in3 to out3 power-good threshold = 87.5% 00 in2 to out2 power-good threshold = 95% 01 in2 to out2 power-good threshold = 92.5% 10 in2 to out2 power-good threshold = 90% 11 in2 to out2 power-good threshold = 87.5% 00 in1 to out1 power-good threshold = 95% 01 in1 to out1 power-good threshold = 92.5% 10 in1 to out1 power-good threshold = 90% 10h 30h [5:0] 11 in1 to out1 power-good threshold = 87.5% table 11. pg threshold settings max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit 24 ______________________________________________________________________________________ abp abp powers the analog circuitry. bypass abp to gnd with a 1f ceramic capacitor installed as close to the device as possible. do not use abp to provide power to external circuitry. configuring the max6876 the max6876 factory-default configuration sets all reg- isters to 00h. this device requires configuration before full power is applied to the system. to configure the max6876, first apply an input voltage greater than 2.7v to one of in1 in4 or v cc (see the powering the max6876 section). next, transmit data with the serial interface. use the block write protocol to quickly config- ure the device. write to the configuration registers first, to ensure the device is configured properly. after com- pleting the setup procedure, use the read word proto- col to read back the data from the configuration registers. lastly, use the write word protocol to write this data to the eeprom registers. after completing the eeprom register configuration, apply full power to the system to begin normal operation. the nonvolatile eeprom stores the latest configuration upon removal of power (table 14). software reboot a command code of c4h initiates a software reboot. a software reboot allows the user to restore the eeprom configuration to the volatile registers without cycling the power supplies. register address eeprom memory address bit range description [7:6] bit [7:6] 00 in4 to out4 overcurrent threshold = 97.5% 01 in4 to out4 overcurrent threshold = 95% 10 in4 to out4 overcurrent threshold = 92.5% 11 in4 to out4 overcurrent threshold = 90% bit [5:4] 00 in3 to out3 overcurrent threshold = 97.5% 01 in3 to out3 overcurrent threshold = 95% 10 in3 to out3 overcurrent threshold = 92.5% 11 in3 to out3 overcurrent threshold = 90% bit [3:2] 00 in2 to out2 overcurrent threshold = 97.5% 01 in2 to out2 overcurrent threshold = 95% 10 in2 to out2 overcurrent threshold = 92.5% 11 in2 to out2 overcurrent threshold = 90% 0dh 2dh [5:0] bit [1:0] 00 in1 to out1 overcurrent threshold = 97.5% 01 in1 to out1 overcurrent threshold = 95% 10 in1 to out1 overcurrent threshold = 92.5% 11 in1 to out1 overcurrent threshold = 90% bit [7:6] 00 overcurrent timer value = 12.5ms 01 overcurrent timer value = 50ms 10 overcurrent timer value = 100ms 11 overcurrent timer value = 200ms bit 5 if 1, overcurrent monitoring on out1 is enabled if 0, no overcurrent monitoring on out1 bit 4 if 1, overcurrent monitoring on out2 is enabled if 0, no overcurrent monitoring on channel 1 bit 3 if 1, overcurrent monitoring on out3 is enabled if 0, no overcurrent monitoring on out3 0eh 2eh [7:1] bit 2 if 1, overcurrent monitoring on out4 is enabled if 0, no overcurrent monitoring on out4 table 12. oc threshold settings max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit ______________________________________________________________________________________ 25 smbus/i 2 c-compatible serial interface the max6876 features an i 2 c/smbus-compatible 2- wire serial interface consisting of a serial data line (sda) and a serial clock line (scl). sda and scl facili- tate bidirectional communication between the max6876 and the master device at clock rates up to 400khz. figure 10 shows the 2-wire interface timing diagram. the max6876 is transmit/receive slave-only, relying upon a master device to generate a clock sig- nal. the master device (typically a microcontroller) initi- ates a data transfer on the bus and generates scl to permit that transfer. a master device communicates to the max6876 by transmitting the proper address followed by command and/or data words. each transmit sequence is framed by a start (s) or repeated start (sr) condition and a stop (p) condition. each word transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse. scl is a logic input, while sda is an open-drain input/output. scl and sda both require external pullup resistors to generate the logic-high voltage. use 4.7k ? for most applications. bit transfer each clock pulse transfers one data bit. the data on sda must remain stable while scl is high (figure 11); otherwise, the max6876 registers a start or stop condition (figure 12) from the master. sda and scl idle high when the bus is not busy. start and stop conditions both scl and sda idle high when the bus is not busy. a master device signals the beginning of a transmis- sion with a start (s) condition (figure 8) by transition- ing sda from high to low while scl is high. the master device issues a stop (p) condition (figure 8) by transi- tioning sda from low to high while scl is high. a stop condition frees the bus for another transmission. the bus remains active if a repeated start condition is generated, such as in the block read protocol (see figure 11). early stop conditions the max6876 recognizes a stop condition at any point during transmission except if a stop condition occurs in the same high pulse as a start condition. this condi- tion is not a legal i 2 c format; at least one clock pulse must separate any start and stop condition. register address eeprom memory address bit range description bit 7 if 1, out1 also controls reset if 0, out1 does not control reset bit 6 if 1, out2 also controls reset if 0, out2 does not control reset bit 5 if 1, out3 also controls reset if 0, out3 does not control reset bit 4 if 1, out4 also controls reset if 0, out4 does not control reset 11h 31h [7:1] bit [3:1] 000 reset timer value = 25s 001 reset timer value = 12.5ms 010 reset timer value = 25.0ms 011 reset timer value = 50.0ms 100 reset timer value = 100.0ms 101 reset timer value = 200.0ms 110 reset timer value = 400.0ms 111 reset timer value = 1600.0ms table 13. program reset max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit 26 ______________________________________________________________________________________ registers descriptions input undervoltage thresholds (registers 00h to 03h) input undervoltage thresholds (0.5v to 3.04v in 10mv increments or 1.0v to 5.5v in 20mv increments). each channel s range is selected with register 08h. input overvoltage thresholds (registers 04h to 07h) input overvoltage thresholds (0.5v to 3.04v in 10mv increments or 1.0v to 5.5v in 20mv increments). each channel s range is selected with register 08h. tracking/sequencing modes selects if outputs are to be sequenced or tracked. sequencing/tracking modes are defined by 4 bits for each out voltage of register 0bh and 0ch (see the track/sequence section). tracking/sequencing power-up/down slew rate selectable output slew rate for power-up/down mode. selected slew is overwritten during tracking faults. power-up/down slew rate is selected by bit [6:7] of register 12h. power-up delay period power-up sequencing delay. selects delay time for sequencing each supply. programmable delays are selected with bit [5:7] of register 0fh. power-down sequence/track behavior selectable power-down operation. chooses if output voltages should be brought down in the reverse sequence from power-up mode selections or if power supplies should be simultaneously fast powered down (selected with bit 7 register 13h). out pulldown enable selects if out_ should be internally pulled to gnd when in fast shutdown or tracking fault mode (selected with bit [6:3] register 13h). single/multiple device application selects if the device will be used alone or in a master/slave application. if a single application, the device can be operated in mixed sequencing/tracking modes. if multi- device application, the device can be operated in tracking mode only (selected with bit [7:6] register 09h). 00: single device 11: master device 01 or 10: slave device over cur r ent thr eshol d s el ects in _- to- ou t_ thr eshol d vol tag e for over cur r ent m oni tor i ng for each channel ( r eg i ster 0d h) . power-good threshold selects in_-to-out_ threshold voltage for power-good monitoring for each channel (register 10h). overcurrent assert select s el ects w hi ch over cur r ent m oni tor s w i l l asser t the oc outp ut ( sel ected b y b i t [ 5:2] of r eg . 0e h) . overcurrent filter period s el ects the fi l ter ti m e for the over cur r ent m oni tor s. o c w i l l not asser t unti l the over cur r ent cond i ti on has exi sted l ong er than the sel ected fi l ter p er i od ( sel ected b y b i t [ 7:6] of r eg . 0e h) . fault timeout period selects the timeout period for sequencing/tracking completion. if sequencing/tracking operation is not complete before the fault timeout period, a fault alert will be signaled and all supplies will be powered down (selected by bit [7:4] of reg. 0ah). fault behavior selects how the device should operate during faults. options include latch-off after fault or autoretry after fault. autoretry delay is selectable (selected by bit 5 of reg. 09h). reset assert select s el ects w hi ch o u t d etector s w i l l asser t the re se t outp ut ( sel ected b y b i t [ 7:4] of r eg . 11h) . reset timeout period select selects the reset timeout period (selected by bit [3:1] of reg. 11h). enable the part with i 2 c interface bit 0 and bit 1 of register 09h allows a micro to turn the max6876 on/off with the i 2 c interface. while 09h[1] is 0, the part will ignore any enable command from i 2 c. if 09h[1] is set to 1, then 09h[0] has to be 1 to enable the part to power on. table 14. registers summary max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit ______________________________________________________________________________________ 27 repeated start conditions a repeated start (sr) condition may indicate a change of data direction on the bus. such a change occurs when a command word is required to initiate a read operation (see figure 12). sr may also be used when the bus master is writing to several i 2 c devices and does not want to relinquish control of the bus. the max6876 serial interface supports continuous write operations with or without an sr condition separating them. continuous read operations require sr condi- tions because of the change in direction of data flow. acknowledge the acknowledge bit (ack) is the 9th bit attached to any 8-bit data word. the receiving device always gen- erates an ack. the max6876 generates an ack when receiving an address or data by pulling sda low during the 9th clock period (figure 13). when transmitting data, such as when the master device reads data back from the max6876, the device waits for the master device to generate an ack. monitoring ack allows for detection of unsuccessful data transfers. an unsuc- cessful data transfer occurs if the receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. the max6876 generates a nack after the slave address during a software reboot, while writing to the eeprom, or when receiving an illegal memory address. stop condition repeated start condition start condition t high t low t r t f t su:dat t su:sta t su:sto t hd:sta t buf t hd:sta t hd:dat scl sda start condition figure 10. serial-interface timing details data line stable, data valid sda scl change of data allowed figure 11. bit transfer p s start condition sda scl stop condition figure 12. start and stop conditions max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit 28 ______________________________________________________________________________________ slave address the max6876 slave address conforms to the following table: sa7 sa4 represent the standard 2-wire interface address (1010) for devices with eeprom. sa3 and sa2 correspond to the a1 and a0 address inputs of the max6876 (hardwired as logic low or logic high). sa0 is a read/write flag bit (0 = write, 1 = read). the a0 and a1 address inputs allow up to four max6876s to connect to one bus. connect a0 and a1 to gnd or to hbp (see figure 14). send byte the send byte protocol allows the master device to send one byte of data to the slave device (see figure 15). the send byte presets a register pointer address for a sub- sequent read or write. the slave sends a nack instead of an ack if the master tries to send an address that is not allowed. if the master sends c0h or c1h, the data is ack, because this could be the start of the write block or read block. if the master sends a stop condition, the internal address pointer does not change. if the master sends c4h, this signifies a software reboot. the send byte procedure follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends an 8-bit data byte. 5) the addressed slave asserts an ack on sda. 6) the master sends a stop condition. write byte/word the write byte/word protocol allows the master device to write a single byte in the register bank, preset an eeprom (configuration or user) address for a subse- quent read, or to write a single byte to the configuration eeprom (see figure 15). the write byte/word proce- dure follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends an 8-bit command code. 5) the addressed slave asserts an ack on sda. 6) the master sends an 8-bit data byte. 7) the addressed slave asserts an ack on sda. scl 1 s 2 89 sda by transmitter sda by receiver start condition clock pulse for acknowledge figure 13. acknowledge sa7 (msb) sa6 sa5 sa4 sa3 sa2 sa1 sa0 (lsb) 1010 a1 a0 xr/ w = don t care. max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit ______________________________________________________________________________________ 29 8) the master sends a stop condition or sends another 8-bit data byte. 9) the addressed slave asserts an ack on sda. 10) the master sends a stop condition. to write a single byte to the register bank, only the 8-bit command code and a single 8-bit data byte are sent. the command code must be in the range of 00h to 13h to write on ram or 20h to 33h to write on eeprom. the data byte is written to the register bank if the command code is valid. the slave generates a nack at step 5 if the command code is invalid. block write the block write protocol allows the master device to write a block of data (1 to 16 bytes) to the eeprom or to the register bank (see figure 15). the destination address must already be set by the send byte or write byte protocol. if the number of bytes to be written caus- es the address pointer to exceed 13h for the configura- tion register (or 33h for the configuration eeprom), the address pointer stays at 13h (or 33h), overwriting this memory address with the remaining bytes of data. the last data byte sent is stored at register address 13h (or 33h). the block write procedure follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends the 8-bit command code for block write (83h). 5) the addressed slave asserts an ack on sda. 6) the master sends the 8-bit byte count (1 to 16 bytes), n. 7) the addressed slave asserts an ack on sda. 8) the master sends 8 bits of data. 9) the addressed slave asserts an ack on sda. 10) repeat steps 8 and 9 n - 1 times. 11) the master generates a stop condition. block read the block read protocol allows the master device to read a block of 16 bytes from the eeprom or register bank (see figure 15). read fewer than 16 bytes of data by issuing an early stop condition from the master, or by generating a nack with the master. the send byte or write byte protocol predetermines the destination address with a command code of c1h. the block read procedure follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends 8 bits of the block read com- mand (c1h). 5) the slave asserts an ack on sda, unless busy. sda scl 1 msb lsb start 01 0 a1 a0 xr/w ack figure 14. slave address max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit 30 ______________________________________________________________________________________ write byte format s address 7 bits send byte format wr ack data 8 bits ack p data byte?resets the internal address pointer. write word format s address wr ack ack ack ack command data data p 7 bits 8 bits 8 bits 8 bits slave address equivalent to chip- select line of a 3- wire interface. write address of the register you are writing to. data byte data goes into the register set by the command. block write format s address wr ack command ack byte count= n ack data byte 1 ack data byte ... ack data byte n ack p 7 bits 8 bits 8 bits 8 bits 8 bits slave address equivalent to chip- select line of a 3- wire interface. command byte prepares device for block operation. data byte?ata goes into the register set by the command byte. block read format s address wr ack command ack sr address wr ack 8 bits byte count= 16 ack data byte 1 ack data byte ... ack data byte n ack p 7 bits 8 bits 7 bits 10h 8 bits 8 bits 8 bits slave address equivalent to chip- select line of a 3- wire interface. command byte prepares device for block operation. slave address equivalent to chip- select line of a 3- wire interface. data byte?ata goes into the register set by the command byte. s = start condition. p = stop condition. shaded = slave transmission. sr = repeated start condition. slave address equivalent to chip- select line of a 3- wire interface. s address wr ack command ack data ack p 7 bits 8 bits 8 bits slave address equivalent to chip- select line of a 3- wire interface. command byte selects register you are writing to. data byte?ata goes into the register set by the command. 0 0 00 0 0 data byte data goes into the next register set by the command. figure 15. smbus/i 2 c protocols max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit ______________________________________________________________________________________ 31 6) the master generates a repeated start condition. 7) the master sends the 7-bit slave address and a read bit (high). 8) the slave asserts an ack on sda. 9) the slave sends the 8-bit byte count (16). 10) the master asserts an ack on sda. 11) the slave sends 8 bits of data. 12) the master asserts an ack on sda. 13) repeat steps 8 and 9 fifteen times. 14) the master generates a stop condition. address pointers use the send byte protocol to set the register address pointers before read and write operations. for the con- figuration registers, valid address pointers range from 00h to 13h. register addresses outside of this range result in a nack being issued from the max6876. when using the block write protocol, the address point- er automatically increments after each data byte, except when the address pointer is already at 13h. if the address pointer is already 13h, and more data bytes are being sent, these subsequent bytes overwrite address 13h repeatedly, leaving only the last data byte sent stored at this register address. for the configuration eeprom, valid address pointers range from 20h to 33h. when using the block write pro- tocol, the address pointer automatically increments after each data byte, except when the address pointer is already at 33h. if the address pointer is already 33h, and more data bytes are being sent, these subsequent bytes overwrite address 33h repeatedly, leaving only the last data byte sent stored at this register address. configuration eeprom the configuration eeprom addresses range from 20h to 33h. write data to the configuration eeprom to auto- matically set up the max6876 upon power-up. data transfers from the configuration eeprom to the config- uration registers when abp exceeds uvlo during power-up. after abp exceeds uvlo, an internal 1mhz clock starts after a 5s delay, and data transfer begins. data transfer disables access to the configuration reg- isters and eeprom. the data transfer from eeprom to the configuration registers takes 2ms (max). read con- figuration eeprom data at any time after power-up or software reboot. write commands to the configuration eeprom are allowed at any time, unless the configura- tion lock bit is set (see table 15). the maximum cycle time to write a single byte is 11ms (max). configuration register bank and eeprom the configuration registers can be directly modified with the serial interface without modifying the eeprom, after the power-up procedure terminates and the con- figuration eeprom data has been loaded into the con- figuration register bank. use the write byte or block write protocols to write directly to the configuration reg- isters. changes to the configuration registers are lost upon power removal. at device power-up, the register bank loads configura- tion data from the eeprom. configuration data can be directly altered in the register bank during application development, allowing maximum flexibility. transfer the new configuration data byte-by-byte to the configura- tion eeprom with the write byte protocol. the next device power-up or software reboot automatically loads the new configuration (table 16). register address eeprom memory address bit range description if 1, configuration registers are locked 13h 33h 2 if 0, configuration registers unlocked table 15. configuration of lock bit max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit 32 ______________________________________________________________________________________ register address eeprom memory address read/write description 00h 20h r/w in1 undervoltage threshold value (v th ): v th = 1.0 + n x 20mv (if r08[7] = 0) v th = 0.5 + n x 10mv (if r08[7] = 1) where n is the register content decimal representation. note that v th ranges must be 1v to 5.5v and 0.5v to 3.05v, respectively. 01h 21h r/w in2 undervoltage threshold value (v th ): v th = 1.0 + n x 20mv (if r08[6] = 0) v th = 0.5 + n x 10mv (if r08[6] = 1) where n is the register content decimal representation. note that v th ranges must be 1v to 5.5v and 0.5v to 3.05v, respectively. 02h 22h r/w in3 undervoltage threshold value (v th ): v th = 1.0 + n x 20mv (if r08[5] = 0) v th = 0.5 + n x 10mv (if r08[5] = 1) where n is the register content decimal representation. note that v th ranges must be 1v to 5.5v and 0.5v to 3.05v, respectively. 03h 23h r/w in4 undervoltage threshold value (v th ): v th = 1.0 + n x 20mv (if r08[4] = 0) v th = 0.5 + n x 10mv (if r08[4] = 1) where n is the register content decimal representation. note that v th ranges must be 1v to 5.5v and 0.5v to 3.05v, respectively. 04h 24h r/w in1 overvoltage threshold value (v th ): v th = 1.0 + n x 20mv (if r08[7] = 0) v th = 0.5 + n x 10mv (if r08[7] = 1) where n is the register content decimal representation. note that v th ranges must be 1v to 5.5v and 0.5v to 3.05v, respectively. 05h 25h r/w in2 overvoltage threshold value (v th ): v th = 1.0 + n x 20mv (if r08[6] = 0) v th = 0.5 + n x 10mv (if r08[6] = 1) where n is the register content decimal representation. note that v th ranges must be 1v to 5.5v and 0.5v to 3.05v, respectively. 06h 26h r/w in3 overvoltage threshold value (v th ): v th = 1.0 + n x 20mv (if r08[5] = 0) v th = 0.5 + n x 10mv (if r08[5] = 1) where n is the register content decimal representation. note that v th ranges must be 1v to 5.5v and 0.5v to 3.05v, respectively. table 16. register map max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit ______________________________________________________________________________________ 33 register address eeprom memory address read/write description 07h 27h r/w in4 overvoltage threshold value (v th ): v th = 1.0 + n x 20mv (if r08[4] = 0) v th = 0.5 + n x 10mv (if r08[4] = 1) where n is the register content decimal representation. note that v th ranges must be 1v to 5.5v and 0.5v to 3.05v, respectively. bit 7 if 0, 20mv steps in v th setting for in1 if 1, 10mv steps in v th setting for in1 bit 6 if 0, 20mv steps in v th setting for in2 if 1, 10mv steps in v th setting for in2 bit 5 if 0, 20mv steps in v th setting for in3 if 1, 10mv steps in v th setting for in3 bit 4 if 0, 20mv steps in v th setting for in4 if 1, 10mv steps in v th setting for in4 bit 3 uv1 or ov1 fault (read only for register address). if 1, in1 is under undervoltage threshold or over overvoltage threshold. if 0, in1 is over undervoltage threshold and under overvoltage threshold. bit 2 uv2 or ov2 fault (read only for register address). if 1, in2 is under undervoltage threshold or over overvoltage threshold. if 0, in2 is over undervoltage threshold and under overvoltage threshold. bit 1 uv3 or ov3 fault (read only for register address). if 1, in3 is under undervoltage threshold or over overvoltage threshold. if 0, in3 is over undervoltage threshold and under overvoltage threshold. 08h 28h r/w bit 0 uv4 or ov4 fault (read only for register address). if 1, in4 is under undervoltage threshold or over overvoltage threshold. if 0, in4 is over undervoltage threshold and under overvoltage threshold. bit [7:6] if 00 the device configuration is a single device if 01 the device configuration is multiple devices, slave if 10 the device configuration is multiple devices, slave if 11 the device configuration is multiple devices, master bit 5 if 1, latch-on fault if 0, autoretry bit [4:2] 000 autoretry timer value = 25s 001 autoretry timer value = 12.5ms 010 autoretry timer value = 25.0ms 011 autoretry timer value = 50.0ms 100 autoretry timer value = 100.0ms 101 autoretry timer value = 200.0ms 110 autoretry timer value = 400.0ms 111 autoretry timer value = 1600.0ms bit 1 if 1, check i 2 c enable bit if 0, ignore i 2 c enable bit 09h 29h r/w bit 0 if 1 and 09h[1] = 1, i 2 c enabled if 0 and 09h[1] = 1, i 2 c disabled table 16. register map (continued) max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit 34 ______________________________________________________________________________________ register address eeprom memory address read/write description bit [7:6] 00 fault power-up timer value = 25ms 01 fault power-up timer value = 50ms 10 fault power-up timer value = 100ms 11 fault power-up timer value = 200ms bit [5:4] 00 fault power-down timer value = 25ms 01 fault power-down timer value = 50ms 10 fault power-down timer value = 100ms 11 fault power-down timer value = 200ms bit 3 reserved (write 0 s for eeprom writes) bit 2 reserved (write 0 s for eeprom writes) bit 1 reserved (write 0 s for eeprom writes) 0ah 2ah r/w bit 0 reserved (write 0 s for eeprom writes) bit 7 if 1, out4 on ramp 2 bit 6 if 1, out3 on ramp 2 bit 5 if 1, out2 on ramp 2 bit 4 if 1, out1 on ramp 2 bit 3 if 1, out4 on ramp 1 bit 2 if 1, out3 on ramp 1 bit 1 if 1, out2 on ramp 1 0bh 2bh r/w bit 0 if 1, out1 on ramp 1 bit 7 if 1, out4 on ramp 4 bit 6 if 1, out3 on ramp 4 bit 5 if 1, out2 on ramp 4 bit 4 if 1, out1 on ramp 4 bit 3 if 1, out4 on ramp 3 bit 2 if 1, out3 on ramp 3 bit 1 if 1, out2 on ramp 3 0ch 2ch r/w bit 0 if 1, out1 on ramp 3 bit [7:6] 00 in4 to out4 overcurrent threshold = 97.5% 01 in4 to out4 overcurrent threshold = 95% 10 in4 to out4 overcurrent threshold = 92.5% 11 in4 to out4 overcurrent threshold = 90% bit [5:4] 00 in3 to out3 overcurrent threshold = 97.5% 01 in3 to out3 overcurrent threshold = 95% 10 in3 to out3 overcurrent threshold = 92.5% 11 in3 to out3 overcurrent threshold = 90% bit [3:2] 00 in2 to out2 overcurrent threshold = 97.5% 01 in2 to out2 overcurrent threshold = 95% 10 in2 to out2 overcurrent threshold = 92.5% 11 in2 to out2 overcurrent threshold = 90% 0dh 2dh r/w bit [1:0] 00 in1 to out1 overcurrent threshold = 97.5% 01 in1 to out1 overcurrent threshold = 95% 10 in1 to out1 overcurrent threshold = 92.5% 11 in1 to out1 overcurrent threshold = 90% table 16. register map (continued) max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit ______________________________________________________________________________________ 35 register address eeprom memory address read/write description bit [7:6] 00 overcurrent timer value = 12.5ms 01 overcurrent timer value = 50ms 10 overcurrent timer value = 100ms 11 overcurrent timer value = 200ms bit 5 if 1, overcurrent monitoring on out1 is enabled if 0, no overcurrent monitoring on out1 bit 4 if 1, overcurrent monitoring on out2 is enabled if 0, no overcurrent monitoring on out2 bit 3 if 1, overcurrent monitoring on out3 is enabled if 0, no overcurrent monitoring on out3 bit 2 if 1, overcurrent monitoring on out4 is enabled if 0, no overcurrent monitoring on out4 0eh 2eh r/w bit [1:0] not used bit [7:5] 000 gate1-delay timer value = 25s 001 gate1-delay timer value = 12.5ms 010 gate1-delay timer value = 25.0ms 011 gate1-delay timer value = 50.0ms 100 gate1-delay timer value = 100.0ms 101 gate1-delay timer value = 200.0ms 110 gate1-delay timer value = 400.0ms 111 gate1-delay timer value = 1600.0ms bit 4 not used bit 3 oc1 overcurrent fault (read only for register address). if 1, oc1 is overcurrent. if 0, oc1 is not overcurrent. bit 2 oc2 overcurrent fault (read only for register address). if 1, oc2 is overcurrent. if 0, oc2 is not overcurrent. bit 1 oc3 overcurrent fault (read only for register address). if 1, oc3 is overcurrent. if 0, oc3 is not overcurrent. 0fh 2fh r/w bit 0 oc4 overcurrent fault (read only for register address). if 1, oc4 is overcurrent. if 0, oc4 is not overcurrent. bit [7:6] 00 in4 to out4 power-good threshold = 95% 01 in4 to out4 power-good threshold = 92.5% 10 in4 to out4 power-good threshold = 90% 11 in4 to out4 power-good threshold = 87.5% bit [5:4] 00 in3 to out3 power-good threshold = 95% 01 in3 to out3 power-good threshold = 92.5% 10 in3 to out3 power-good threshold = 90% 11 in3 to out3 power-good threshold = 87.5% bit [3:2] 00 in2 to out2 power-good threshold = 95% 01 in2 to out2 power-good threshold = 92.5% 10 in2 to out2 power-good threshold = 90% 11 in2 to out2 power-good threshold = 87.5% 10h 30h r/w bit [1:0] 00 in1 to out1 power-good threshold = 95% 01 in1 to out1 power-good threshold = 92.5% 10 in1 to out1 power-good threshold = 90% 11 in1 to out1 power-good threshold = 87.5% table 16. register map (continued) max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit 36 ______________________________________________________________________________________ register address eeprom memory address read/write description bit 7 if 1, out1 also controls reset if 0, out1 does not control reset bit 6 if 1, out2 also controls reset if 0, out2 does not control reset bit 5 if 1, out3 also controls reset if 0, out3 does not control reset bit 4 if 1, out4 also controls reset if 0, out4 does not control reset bit [3:1] 000 reset timer value = 25s 001 reset timer value = 12.5ms 010 reset timer value = 25.0ms 011 reset timer value = 50.0ms 100 reset timer value = 100.0ms 101 reset timer value = 200.0ms 110 reset timer value = 400.0ms 111 reset timer value = 1600.0ms 11h 31h r/w bit 0. if 1, selects external reference, if 0 internal reference selected bit [7:6] 00 track/sequence slew rate (rise or fall) = 800v/s 01 track/sequence slew rate (rise or fall) = 400v/s 10 track/sequence slew rate (rise or fall) = 200v/s 11 track/sequence slew rate (rise or fall) = 100v/s bit [5:3] not used bit 2 reserved (write 0 s for eeprom writes) bit 1 reserved (write 0 s for eeprom writes) 12h 32h r/w bit 0 reserved (write 0 s for eeprom writes) bit 7 if 1, reverse order of track/sequence power-down if 0, gate_ fast pulldown bit 6 if 1, out1 pulldown with 100 ? if 0, out1 100 ? pulldown disabled bit 5 if 1, it is possible to discharge out2 with a pulldown if 0, no pulldown is allowed bit 4 if 1, it is possible to discharge out3 with a pulldown if 0, no pulldown is allowed bit 3 if 1, it is possible to discharge out4 with a pulldown if 0, no pulldown is allowed bit 2 if 1, configuration registers are locked if 0, configuration registers unlocked 13h 33h r/w bit [1:0] not used 14h 34h reserved. should not be overwritten. 15h 35h reserved. should not be overwritten. 16h 36h reserved. should not be overwritten. table 16. register map (continued) max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit ______________________________________________________________________________________ 37 register address eeprom memory address read/write description 17h 37h reserved. should not be overwritten. reserved. should not be overwritten. 18h 38h reserved. should not be overwritten. reserved. should not be overwritten. 19h 39h reserved. should not be overwritten. reserved. should not be overwritten. 1ah 3ah reserved. should not be overwritten. reserved. should not be overwritten. 1bh 3bh reserved. should not be overwritten. reserved. should not be overwritten. 1ch 3ch reserved. should not be overwritten. reserved. should not be overwritten. reserved. should not be overwritten. reserved. should not be overwritten. 1dh 3dh reserved. should not be overwritten. 1eh 3eh reserved. should not be overwritten. reserved. should not be overwritten. reserved. should not be overwritten. reserved. should not be overwritten. reserved. should not be overwritten. reserved. should not be overwritten. reserved. should not be overwritten. reserved. should not be overwritten. 1fh 3fh reserved. should not be overwritten. table 16. register map (continued) applications information layout and bypassing for better noise immunity, bypass each of the voltage- detector inputs to gnd with 0.1f capacitors installed as close to the device as possible. bypass abp to gnd with 1f capacitors installed as close to the device as possible. abp is an internally generated voltage and should not be used to supply power to external circuitry. configuration latency period a delay of less than 5s occurs between writing to the configuration registers and the time when these changes actually take place, unless when changing one of the voltage detector s thresholds. changing a volt- age-detector threshold typically takes 150s. when changing eeprom contents, software reboot or cycling of power is required for these changes to transfer to volatile memory. chip information process: bicmos max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit 38 ______________________________________________________________________________________ in1 gate3 gate2 gate1 in4 in3 in2 gate4 v cc enable fault synch hold trken abp pg_ gnd sda scl a0 a1 out1 rem out2 out4 out3 reset out1 out2 out3 out4 v pullup max6876 in1 in2 in3 in4 in1 gate3 gate2 gate1 in4 in3 in2 gate4 enable out1 out2 out3 in1 in2 in3 in4 out4 abp trken synch (out) hold fault v cc master 5v 3.0v 1v 1.8v out1 out2 out3 out4 in1 gate3 gate2 gate1 in4 in3 in2 gate4 enable out1 out2 out3 in5 in6 in7 in8 out4 abp trken slave 3.3v 2.5v 0.75v 1.5v out5 out6 out7 out8 synch (in) hold fault v cc always on 3.3v note: configuring the max6876 for master/slave operation. typical application circuits max6876 eeprom-programmable, quad, power-supply tracker/sequencer circuit maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 39 ? 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qfn thin 6x6x0.8 .eps e e l l a1 a2 a e/2 e d/2 d e2/2 e2 (ne-1) x e (nd-1) x e e d2/2 d2 b k k l c l c l c l c l e 1 2 21-0141 package outline 36, 40, 48l thin qfn, 6x6x0.8mm l1 l e 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 6. nd and ne refer to the number of terminals on each d and e side respectively. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 9. drawing conforms to jedec mo220, except for 0.4mm lead pitch package t4866-1. 7. depopulation is possible in a symmetrical fashion. 3. n is the total number of terminals. 2. all dimensions are in millimeters. angles are in degrees. 1. dimensioning & tolerancing conform to asme y14.5m-1994. notes: 10. warpage shall not exceed 0.10 mm. e 2 2 21-0141 package outline 36, 40, 48l thin qfn, 6x6x0.8mm |
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